Let spacing is 3 units and via

Let us see how to calculate the standard cell height, pitch, size of PMOS and NMOS  for a 9 track library. Let the metal width be 4 units,minimum metal to metal spacing is 3 units and via overhang be 2.Pitch = 21/2(metal width)+ metal-to-metal spacing+Via overhead. Using this formula, Pitch = 11 units.Standard cell height = Pitch * (N-1) where N represents the number of tracks. This  sums to 56 units.In a layout, the cells will be arranged one above the other, in such away that they can share one common VDD and VSS. Fig. 2 depicts two cells(can be any cells) abutted in such a way that they share the same VDD.Fig. 2 Calculation of Standard cell heightLet us take the ? ratio as 1.5. Hence, Wp=1.5Wn. Below given are the variables used for calculating the standard cell height :p = Poly overhang, here it is 2 units.x = Minimum well to well spacing required between the two cells, here it is 12 units.y = We need to leave some space to avoid DRC violation between two different cells abutted on VDD and VSS. This comes to 1.5 units.Wp = Width of PMOS.Wn = Width of NMOS.Height of the standard cell , Wp+Wn+x+2y+2p = 56units.Using this formula, Wn is calculated as 15units and Wp is calculated as 22units. Similarly we can calculate Wn and Wp values for different libraries.If we compare 7T and 11T, 11T is faster and will give better performance because the area for 11T is more so that we can place higher drive strength transistors in it. Using 11T library we can achieve higher utilizations.11T library are used for better performance.7T library are used for higher density & low power.Cells in generic libraryBasic gates (AND, OR, NAND, NOR, INV, EXOR, EXNOR)MUXHA, FASpecial cells (Fillers, Tap cells, End Cap, De Caps)Tie CellsMetal Eco-able cellsAOIOAIBoolean function cellsFlops (Normal D flip flop, Scan-able flop with set / reset)Clock gatePower management cellsIsolation cellUsed to isolate the output of OFF domain.Allowing the floating output value of OFF domain (in off state) to be connected with the ON domain will result inFlow of crowbar current, resulting in the increase of power consumption.Improper functioning of ON domain which may cause meta-stability.Also known as clamp cells, because they are used to clamp the intermediate voltage levels to either 0 or 1.Isolation cells are designed either using OR gate (clamp 1) or AND gate (clamp 0).In case of microcontroller, when the processor goes to off mode, we use isolation cells to isolate the processor core from other modules.Isolation cells can be placed either in OFF domain or ON domain.When there are multiple fanouts from the OFF domain placing one isolation cell in the OFF domain will isolate multiple sinks. Power must be provided from always ON supply/sink domain power supply which is challenging.Isolation cells if placed in ON domain don’t require secondary power supply.Fig2: Isolation cellLevel ShifterLevel shifter cell is used to shift a signal voltage from one voltage domain to another.These cells are required when the chip is operating at multiple voltage domains.The difference in voltage range may cause unreliable functioning of destination domain hence, level shifters cells are inserted in the voltage domain crossing.Fig3: Level shifterPower gate / switchThe factors which are to be considered while designing power switch network are:When they are ON, their Vt will be so low whereas when they are OFF, their Vt will be so high.Power gates are designed with the help of multi threshold CMOS.Power gating is a technique used in IC designs to reduce power consumption by shutting off the power to blocks of the circuit that are not in use.Power gates are used for power gating.Rush current: Rush current is the current drawn by a component during its initial power up to charge its internal capacitors. When a power domain is powered up from shutdown all the capacitors in the power domain starts to charge. The amount of current drawn will be huge as all the capacitors start to charge which will result in sudden rush of current. This rush current can damage the power switch network. For this we usually design the power switch network in daisy chain fashion.Leakage current: The number of power switches used to implement power switch network should be optimal because if more power switches are there leakage current will be more.Ramp up time: It is the time required to power up an off component so the power switch network should be designed in such a way that the ramp up time is less. It can be achieved by increasing the number of power switches.Retention flopRetention flops are always ON flops which are used to retain the data when a power domain goes to OFF mode.Secondary power supply is used to power these flops.A retention flop is a combination of regular flop and state saving latch.Special cellsTap cellsTap cells are used to provide substrate connection.They are used to avoid latch-up.They connect n-well to VDD and p-sub to VSS.They are inserted in layout at regular intervals based on tap rules (tap to gate distance) defined in the technology DRC file.Filler cellsFiller cells are used to provide rail continuity, thereby reducing the DRC violations created by the base.Filler cells are designed in such a way that they contain n-well and p substrate.Metal eco-able cellsThe filler cells which are converted to attain any functionality are called metal eco-able cells.The base layers of both filler cells and metal eco-able cells are same. Some extra metal connections will be added in metal eco-able cells to attain the functionality.Sizes of these cells are more when compared to normal cells of same functionality.For example, consider a design having hold violation after the fabrication. One way to overcome the violation is to delay the data-path. In this case we can convert metal eco-able cells to buffer for the delay. (generally done during re-spin of chip).Antenna diodeDuring fabrication stray charges get accumulated in metal layers. The gate gets ruptured when the amount of these charges are more than threshold. This effect is called antenna effect. The threshold is decided by metal layer area to gate area ratio.To overcome the antenna effect we use antenna diodes.Zener diodes will be connected to the metal layers to remove the excess charges.Fig4: Antenna diodeAnother way to overcome antenna effect is to add jumpers. Use higher metal layers for connection.Fig5: JumperDe cap cells (Decoupling capacitor cells)De cap cells are capacitors added in design between power and ground rails.When there is drop in power rail, these cells act like a battery and maintain the voltage across rails.These cells aids IR drop issue and removes glitches in power.In a design most of the power consumption is done by clock circuits. Assume that all the clock blocks are clustered in an area, then they will consume more power, i.e. they drew more current which will increase IR drop. In this case de cap cells can be used.End cap cellEnd cap cells are added near the end of rows to terminate the rows properly.The n-wells of end cap cells are properly terminated within the cell.Tie cellTie cells are used to avoid direct gate connection to the power or ground network thereby protecting the cell from damage.In your design, some cell inputs may require a logic 0 or logic 1 value. Instead of connecting these to the VDD/VSS rails/rings, you connect them to special cells available in your library called TIE cells.In tie high cell, nmos acts as diode connected and gives logic 0 to the gate of pmos, so we will get logic 1 as output whereas in tie low cell, pmos act as diode connected and gives logic 1 to the gate of nmos, so we will get logic 0 as output.Fig6: Tie cellSpare cellSpare cells are normal standard cells but they act as redundant cells as they are evenly distributed on the chip in anticipation of future ECO i.e, after the tape out.After the tape out, sometimes we may have to make some changes to the design to resolve a bug. In these cases we use the pre existing spare cells in the design.If we carry out the design changes with minimal layer changes, it will save a lot of cost from fabrication point of view as each mask layer has significant cost of its own.Spare cell inputs are connected to VDD/GND when they are placed in the design and their outputs are left floating.If they are required to be used, then their inputs are disconnected from VDD/GND and connected to functional logic in ECO mode.